1、除法运算的Verilog实现（累加比较法）
2、module mydiv(clk, dataa, datab, start, datac); input clk;input [7:0] dataa;//被除数input [7:0] datab;//除数input start;//开始新的运算output [7:0] datac;//商reg [7:0] datac;reg [7:0] cbuf;reg [7:0] temp;always @(posedge clk)beginif(1'b1 == start)begintemp <= 8'd0;cbuf <= 8'd0;endelse if (dataa > temp)begintemp <= temp + datab;cbuf <= cbuf + 8'h01;endelsebegindatac <= cbuf;endendEndmodule
3、直接测频法
4、闸门产生模块/gateout输出1s，clk设为1msmodule gate(cl氯短赤亻k, gateout);input c造婷用痃lk;output gateout;reg [9:0] cnt;reg gatebuf;assign gateout = gatebuf;always @(posedge clk)beginif (10'd999 == cnt)begincnt <= 10'd0;gatebuf <= ~gatebuf; //产生1s闸门endelsebegincnt <= cnt + 10'd1;endendendmodule计数模块说明：闸门信号高有效下进行计数，当闸门信号为低时停止计数并输出计数结果。采用5位十进制计数module cnt(clk, gate, done, dtwo, dthree, dfour, dfive);input clk;input gate;output done;//个位output dtwo;//十位output dthree;//百位output dfour;//千位output dfive;//万位reg [3:0] done, dtwo, dthree, dfour, dfive;reg [3:0] ddone, ddtwo, ddthree, ddfour, ddfive;reg gatebuf;always @(posedge clk)begingatebuf <= gate;endalways @(posedge clk)beginif((gatebuf == 1'b0) && (gate == 1'b1))beginddone <= 4'd1;ddtwo <= 4'd0;ddthree <= 4'd0;ddfour <= 4'd0;ddfive <= 4'd0;endelse if((gatebuf == 1'b1) && (gate == 1'b0))begindone <= ddone;dtwo <= ddtwo;dthree <= ddthree;dfour <= ddfour;dfive <= ddfive;endelse if(gate == 1'b1)beginif (ddone == 4'd9)beginddone <= 4'd0;if (ddtwo == 4'd9)beginddtwo <= 4'd0;if (ddthree == 4'd9)beginddthree <= 4'd0;if (ddfour == 4'd9)beginddfour <= 4'd0;if (ddfive == 4'd9)beginddfive <= 0;endelsebeginddfive <= ddfive + 4'd1;endendelsebeginddfour <= ddfour + 4'd1;endendelsebeginddthree <= ddthree + 4'd1;endendelsebeginddtwo <= ddtwo + 4'd1;endendelsebeginddone <= ddone + 4'd1;endendendendmodule
5、周期测频法
6、计数模块module periodcnt(clk, clkt, cntout,cntok);input clk;//标准时钟信号input clkt;//被测信号output [19:0] cntout;//计数结果输出output cntok;//计数结果输出标志reg [19:0] cntout, cnt;reg cntok, clktbuf;always @(posedge clk)beginclktbuf <= clkt;endalways @(posedge clk)beginif((clkt == 1'b1) && (clktbuf == 1'b0))//在被测信号上升沿输出计数结果并置计数为1begincntout <= cnt;cnt <= 20'd1;cntok <= 1'b1;endelsebegincnt <= cnt + 20'd1;cntok <= 1'b0;endendendmodule除法运算模块module perioddiv(clk, datab, start, datac);input clk;input [19:0] datab;input start;output [19:0] datac;reg [19:0] dataa,datac, databbuf;reg [19:0] cbuf;reg [19:0] temp;reg finish, cntflag;always @(posedge clk)beginif((1'b1 == start) && (finish == 1'b0) && (datab != 20'd0))begindataa <= 1000000;temp <= datab;cbuf <= 20'd1;databbuf <= datab;cntflag <= 1'b1;endelse if ((dataa > temp) && (cntflag == 1'b1) )begintemp <= temp + databbuf;cbuf <= cbuf + 20'd1;finish <= 1'b1;endelsebegindatac <= cbuf;finish <= 1'b0;cntflag <= 1'b0;endendendmodule
7、等精度测频法
8、预设闸门模块：由标准时钟计数产生module pregate(clk, gateout);input clk稆糨孝汶;output gateout;reg gateout, gatebuf;reg [19:0] cnt;always @(posedge clk)beginif (cnt == 20'd1000)begingatebuf <= ~gatebuf;gateout <= gatebuf;cnt <= 20'd0;endelsebegincnt <= cnt + 20'd1;endendendmodule实际闸门模块：由被测信号来同步预设闸门模块产生module actgate(clk, gatein, gateout);input clk;input gatein;output gateout;reg gateout;always @(posedge clk)begingateout <= gatein;endendmodule计数模块：在实际闸门信号有效时，标准时钟与被测信号同时进行计数；在闸门信号结束时输出计数结果module cnt(clk, gate, cntout);input clk;input gate;output [19:0] cntout ;reg [19:0] cnt, cntout;reg gatebuf;always @(posedge clk)begingatebuf <= gate;endalways @(posedge clk)beginif((gate == 1'b1) && (gatebuf == 1'b0))begincnt <= 20'd1;endelse if((gate == 1'b0) && (gatebuf == 1'b1))begincntout <= cnt;endelse if(gatebuf == 1'b1)begincnt <= cnt + 20'd1;endendendmodule频率计数模块：根据公式计算module frediv(clk, datat,datas, freout);input clk;input [19:0] datat;input [19:0] datas;output [19:0] freout;reg [19:0] datam,freout, databbuf;reg [19:0] cbuf;reg [19:0] temp;reg finish, cntflag;always @(posedge clk)beginif((finish == 1'b0) && (datas != 20'd0) && (datat != 20'd0))begindatam <= 20'd10000 * datat;temp <= datas;cbuf <= 20'd1;databbuf <= datas;cntflag <= 1'b1;finish <= 1'b1;endelse if ((datam > temp) && (cntflag == 1'b1) )begintemp <= temp + databbuf;cbuf <= cbuf + 20'd1;endelsebeginfreout <= cbuf;finish <= 1'b0;cntflag <= 1'b0;endendendmodule